1. Field of the Invention
The present invention relates to flash memory, and more particularly to the reading of flash memory.
2. Description of Related Art
Single-bit serial and multiple-bit serial Flash memory has become popular due to low pin count and simplicity of the interface. The simplest interface is the one-bit Serial Peripheral Interface (“SPI”). The one-bit SPI protocol involves sending a 8-bit command, address bytes, and optional dummy bytes by a user to the SPI Flash memory device, and in response the SPI Flash memory device returns data to the user. A unique 8-bit command may identify a read, an erase/program, or another appropriate operation. Multiple-bit serial interfaces such as SPI-Dual, SPI-Quad, and the Quad Peripheral Interface (“QPI”) have been developed for high performance system applications which require fast read performance. In the SPI-Quad interface, an 8-bit command is provided serially one bit at a time, but all subsequent fields (e.g. address, optional dummy bytes, and data) are done on a 4-bit (Quad) serial basis to improve read thru-put. In the QPI interface, all of the fields (e.g. 8-bit command, address, optional dummy bytes, and data) are done in 4-bit serial. As such, the QPI interface provides an 8-bit command in two clock cycles, whereas the SPI-Quad needs eight clock cycles. By reducing the number of clock cycles needed to provide the read command, the QPI interface achieves better read performance compared to both SPI and SPI-Quad interface. Various multiple-bit serial Flash interface protocols are described in, for example, U.S. Pat. No. 7,558,900 issued Jul. 7, 2009 to Jigour et al.
In an attempt to minimize latency, different read commands are used for different address boundaries, and these different commands use different numbers of dummy bytes (which may include mode bytes) depending on the address boundaries; see FIG. 1 and FIG. 2. In the SPI Quad interface, for example, an 8-bit command is provided to the Flash memory device in accordance with the 1-bit serial interface (e.g. by I/O0), but subsequent interfacing is done in accordance with the 4-bit Quad interface (e.g. by I/O0-I/O3 (not shown)). The command and address are provided to the SPI Flash memory device and latched on the “rising edge” of clock, and Data-out is provided by the SPI Flash device on the “falling edge” of clock.
FIG. 1 shows a type of SPI-Quad command known as EBh_SPI (or Fast read Quad I/O) which does not impose an address restriction since it assumes a byte boundary. This command includes 6 dummy clocks. FIG. 2 shows a type of SPI-Quad command known as E7h_SPI (or Word read Quad I/O) which restricts the address to a word boundary (A0=0). Because of the address boundary restriction explicit in the command, this need include only 4 dummy bytes. Therefore, the E7h_SPI command provides higher system read performance as measured by reduced latency compared to the EBh_SPI command.
Various modes of operation, including SPI, SPI-Quad, and a full Enhanced SPI mode which supports multiple-bit serial input and output, are described in U.S. Pat. No. 7,558,900, issued Jul. 7, 2009 to Jigour et al.
Nonetheless, even higher system read performance is desirable for certain applications.